EXP-10 SIMULATION OF VHDL CODE FOR DELAY

AIM:
       To develop a VHDL code for making a delayed output with variable delay.

APPARATUS REQUIRED:
      Xilinx V14.7 software

FLOW CHART:

PROGRAMS CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity first is

port ( clock : in std_logic;
a : out std_logic);

end first;

architecture Behavioral of first is

begin
process(clock)

variable i : integer := 0;

begin

if clock'event and clock = '1' then
if i < 50 then

i := i + 1;

a <= '1';

elsif i >= 50 and i < 100 then

i := i + 1;

a <= '0';

elsif i = 100 then

i := 0;

end if;
end if;
end process;
end Behavioral;

SIMULATION OUTPUT:

PROCEDURE:
Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next >  select proper project settings> we use spartan 3E trainer kit.

Step2: next > finish > go to project > new source > select VHDL module > create file name> next > select input and output > next > finish> write program > if done write programs > click synthesis > right click> run.

Step3: if completed successfully > go to simulation > click source file > right click > new source > select VHDL test bench > create simulation file name > next > select source file > next > finish.

Step4: select simulation file > Isim simulator > click behavioral check syntax > right click > run > if successfully completed. click simulation behavioral > right click > run > wait few seconds > will open new tap.

Step5: click object name > right click > select force clock >

Step6: click Run All > click zoom to full view > check simulation output in this screen
         
 Note: if you want image file > click print screen  > open MS paint > cnt +v > save
           if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok