EXP-6 VHDL IMPLEMENTATION OF DEMULTIPLEXER

AIM:
       To implement a 1:8 demultiplexer in FPGA kit using switches(inputs) and LEDs(outputs).

APPARATUS REQUIRED:
       Xilinx V14.7 software
       FPGA Trainer kit

LOGIC DIAGRAMS:

TRUTH TABLES:

FLOW CHART:

PROGRAMS CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity demux_m is
    Port ( i : in  STD_LOGIC;
           s : in  STD_LOGIC_VECTOR (2 downto 0);
           o : out  STD_LOGIC_VECTOR (7 downto 0));
end demux_m;

architecture Behavioral of demux_m is

begin

o(0) <= i and not s(2) and not s(1) and not s(0);
o(1) <= i and not s(2) and not s(1) and s(0);
o(2) <= i and not s(2) and s(1) and not s(0);
o(3) <= i and not s(2) and s(1) and s(0);
o(4) <= i and s(2) and not s(1) and not s(0);
o(5) <= i and s(2) and not s(1) and s(0);
o(6) <= i and s(2) and s(1) and not s(0);
o(7) <= i and s(2) and s(1) and s(0);

end Behavioral;

PROCEDURES:
Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next >  select proper project settings> we use spartan 3E trainer kit.

Step2: next > finish > go to project > new source > select VHDL module > create file name> next > select input and output > next > finish> write program > if done write programs > click synthesis > right click> run.

Step3: go to user constraints > select I/O pin planning and right click > run > yes. wait few seconds. will open new tap like this.

Step4:  Assign input and output of the trainer kit pinouts > go to file > select save to constraints and close that tap. select implementation design and right click > run. select generate programming and right click > run. if you completed those three option with green tik. select configure device and right click >run. will open new tap. double click boundary scan >  ok. connect FPGA Trainer kit to PC system through parallel port or usb > right click centre point of the blue colour line > select initialize chain > then connected your FPGA Trainer kit.

Step5: open .bit file and load it > now you check the output result of the  FPGA Trainer kit.

NOTE: if you want image file > click print screen  > open MS paint > cnt +v > save
           if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok