EXP-7 VHDL IMPLEMENTATION OF 7SEGMENT DECODER

AIM:
       To implement a BCD to seven segment  decoder in VHDL.

APPARATUS REQUIRED:
       Xilinx V14.7 software
       FPGA Trainer kit

LOGIC DIAGRAMS:

CONNECTION DIAGRAMS:

TRUTH TABLES:
Common Cathode 7segment display truth table.

FLOW CHART:

PROGRAMS CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bcd_m is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : in  STD_LOGIC;
           D : in  STD_LOGIC;
           seg : out  STD_LOGIC_VECTOR (6 downto 0));
end bcd_m;

architecture Behavioral of bcd_m is

begin
process (A,B,C,D)
begin
seg(0) <= (D or (not C and not A) or (C and A) or (C and B));
seg(1) <= (D or (not D and not C) or (not B and not A) or (B and A));
seg(2) <= (not B or C or (not D and A));
seg(3) <= (D or (not C and not A) or (not D and not C and B) or (not D and B and not A) or (C and not B and not A));
seg(4) <= ((not C and A) or (not B and not A));
seg(5) <= ( D or (not B and not A) or (C and not B) or (C and not A));
seg(6) <= (D or (C and not B) or (B and not A) or (not C and B));
end process;

end Behavioral;

PROCEDURES:

Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next >  select proper project settings> we use spartan 3E trainer kit.

Step2: next > finish > go to project > new source > select VHDL module > create file name> next > select input and output > next > finish> write program > if done write programs > click synthesis > right click> run.

Step3: go to user constraints > select I/O pin planning and right click > run > yes. wait few seconds. will open new tap like this.

Step4:  Assign input and output of the trainer kit pinouts > go to file > select save to constraints and close that tap. select implementation design and right click > run. select generate programming and right click > run. if you completed those three option with green tik. select configure device and right click >run. will open new tap. double click boundary scan >  ok. connect FPGA Trainer kit to PC system through parallel port or usb > right click centre point of the blue colour line > select initialize chain > then connected your FPGA Trainer kit.

Step5: open .bit file and load it > now you check the output result of the  FPGA Trainer kit.

NOTE: if you want image file > click print screen  > open MS paint > cnt +v > save
           if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok