AIM:
To design and develop an 1:8 output demultiplexer using VHDL code and simulate it.
APPARATUS REQUIRED:
Xilinx V14.7 Software
LOGIC DIAGRAMS:
TRUTH TABLE:
FLOW CHART:
PROGRAMS CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_m is
Port ( i : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (2 downto 0);
o : out STD_LOGIC_VECTOR (7 downto 0));
end demux_m;
architecture Behavioral of demux_m is
begin
o(0) <= i and not s(2) and not s(1) and not s(0);
o(1) <= i and not s(2) and not s(1) and s(0);
o(2) <= i and not s(2) and s(1) and not s(0);
o(3) <= i and not s(2) and s(1) and s(0);
o(4) <= i and s(2) and not s(1) and not s(0);
o(5) <= i and s(2) and not s(1) and s(0);
o(6) <= i and s(2) and s(1) and not s(0);
o(7) <= i and s(2) and s(1) and s(0);
end Behavioral;
SIMULATION OUTPUT:
PROCEDURES:
Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next > select proper project settings> we use spartan 3E trainer kit.
Step2: next > finish > go to project > new source > select VHDL module > create file name> next > select input and output > next > finish> write program > if done write programs > click synthesis > right click> run.
Step3: if completed successfully > go to simulation > click source file > right click > new source > select VHDL test bench > create simulation file name > next > select source file > next > finish.
Step4: select simulation file > Isim simulator > click behavioral check syntax > right click > run > if successfully completed. click simulation behavioral > right click > run > wait few seconds > will open new tap.
Step5: click object name > right click > select force constant >
Step6: set all input value > click Run for the time specified on the toolbar> check simulation output in this screen
NOTE: if you want image file > click print screen > open MS paint > cnt +v > save
if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok
To design and develop an 1:8 output demultiplexer using VHDL code and simulate it.
APPARATUS REQUIRED:
Xilinx V14.7 Software
LOGIC DIAGRAMS:
TRUTH TABLE:
PROGRAMS CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_m is
Port ( i : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (2 downto 0);
o : out STD_LOGIC_VECTOR (7 downto 0));
end demux_m;
architecture Behavioral of demux_m is
begin
o(0) <= i and not s(2) and not s(1) and not s(0);
o(1) <= i and not s(2) and not s(1) and s(0);
o(2) <= i and not s(2) and s(1) and not s(0);
o(3) <= i and not s(2) and s(1) and s(0);
o(4) <= i and s(2) and not s(1) and not s(0);
o(5) <= i and s(2) and not s(1) and s(0);
o(6) <= i and s(2) and s(1) and not s(0);
o(7) <= i and s(2) and s(1) and s(0);
end Behavioral;
SIMULATION OUTPUT:
PROCEDURES:
Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next > select proper project settings> we use spartan 3E trainer kit.
Step2: next > finish > go to project > new source > select VHDL module > create file name> next > select input and output > next > finish> write program > if done write programs > click synthesis > right click> run.
Step3: if completed successfully > go to simulation > click source file > right click > new source > select VHDL test bench > create simulation file name > next > select source file > next > finish.
Step4: select simulation file > Isim simulator > click behavioral check syntax > right click > run > if successfully completed. click simulation behavioral > right click > run > wait few seconds > will open new tap.
Step5: click object name > right click > select force constant >
Step6: set all input value > click Run for the time specified on the toolbar> check simulation output in this screen
NOTE: if you want image file > click print screen > open MS paint > cnt +v > save
if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok
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