EXP-9 VHDL IMPLEMENTATION OF ENCODER

AIM:
       To implement a decimal to BCD encoder in VHDL using FPGA kit.

APPARATUS REQUIRED:
      Xilinx V14.7 software
      FPGA trainer kit

LOGIC DIAGAMS:

TRUTH TABLE:

FLOW CHART:

PROGRAM CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encoder_m is
    Port (
        D : in  STD_LOGIC_VECTOR (9 downto 0);
           A : out  STD_LOGIC_VECTOR (3 downto 0));
end encoder_m;

architecture Behavioral of encoder_m is

begin
process (D)
begin
case D is
when "0000000001" => A <= "0000";
when "0000000010" => A <= "0001";
when "0000000100" => A <= "0010";
when "0000001000" => A <= "0011";
when "0000010000" => A <= "0100";
when "0000100000" => A <= "0101";
when "0001000000" => A <= "0110";
when "0010000000" => A <= "0111";
when "0100000000" => A <= "1000";
when "1000000000" => A <= "1001";
when others => A <= "1111";
end case;
end process;

end Behavioral;

PROCEDURES:

Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next >  select proper project settings> we use spartan 3E trainer kit.

Step2: next > finish > go to project > new source > select VHDL module > create file name> next > select input and output > next > finish> write program > if done write programs > click synthesis > right click> run.

Step3: go to user constraints > select I/O pin planning and right click > run > yes. wait few seconds. will open new tap like this.

Step4:  Assign input and output of the trainer kit pinouts > go to file > select save to constraints and close that tap. select implementation design and right click > run. select generate programming and right click > run. if you completed those three option with green tik. select configure device and right click >run. will open new tap. double click boundary scan >  ok. connect FPGA Trainer kit to PC system through parallel port or usb > right click centre point of the blue colour line > select initialize chain > then connected your FPGA Trainer kit.

Step5: open .bit file and load it > now you check the output result of the  FPGA Trainer kit.

NOTE: if you want image file > click print screen  > open MS paint > cnt +v > save
           if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok