AIM:
To simulate an 8-bit multiplexer by using the port map with 2-bit multiplexer.
APPARATUS REQUIRED:
Xilinx V14.7 Software
LOGIC DIAGRAMS:
1. 2:1 Multiplexer:
2. Symbol:
3. 8:1 Multiplexer using 2:1 Multiplexer:
TRUTH TABLES:
FLOW CHART:
PROGRAMS:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_m is
Port ( I0,I1,I2,I3,I4,I5,I6,I7 : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR (2 downto 0);
Y8 : out STD_LOGIC);
end mux_m;
architecture Behavioral of mux_m is
begin
process (I0,I1,I2,I3,I4,I5,I6,I7, Sel)
begin
case Sel is
when "000" => Y8 <= I0;
when "001" => Y8 <= I1;
when "010" => Y8 <= I2;
when "011" => Y8 <= I3;
when "100" => Y8 <= I4;
when "101" => Y8 <= I5;
when "110" => Y8 <= I6;
when "111" => Y8 <= I7;
when others => null;
end case;
end process;
end Behavioral;
PROCEDURES:
Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next > select proper project settings> we use spartan 3E trainer kit.
Step2: next > finish > go to project > new source > select VHDL module > create file name> next > select input and output > next > finish> write program > if done write programs > click synthesis > right click> run.
Step3: if completed successfully > go to simulation > click source file > right click > new source > select VHDL test bench > create simulation file name > next > select source file > next > finish.
Step4: select simulation file > Isim simulator > click behavioral check syntax > right click > run > if successfully completed. click simulation behavioral > right click > run > wait few seconds > will open new tap.
Step5: click object name > right click > select force constant >
Step6: set all input value > click Run for the time specified on the toolbar> check simulation output in this screen
NOTE: if you want image file > click print screen > open MS paint > cnt +v > save
if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok
To simulate an 8-bit multiplexer by using the port map with 2-bit multiplexer.
APPARATUS REQUIRED:
Xilinx V14.7 Software
LOGIC DIAGRAMS:
1. 2:1 Multiplexer:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_m is
Port ( I0,I1,I2,I3,I4,I5,I6,I7 : in STD_LOGIC;
Sel : in STD_LOGIC_VECTOR (2 downto 0);
Y8 : out STD_LOGIC);
end mux_m;
architecture Behavioral of mux_m is
begin
process (I0,I1,I2,I3,I4,I5,I6,I7, Sel)
begin
case Sel is
when "000" => Y8 <= I0;
when "001" => Y8 <= I1;
when "010" => Y8 <= I2;
when "011" => Y8 <= I3;
when "100" => Y8 <= I4;
when "101" => Y8 <= I5;
when "110" => Y8 <= I6;
when "111" => Y8 <= I7;
when others => null;
end case;
end process;
end Behavioral;
SIMULATION OUTPUT:
Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next > select proper project settings> we use spartan 3E trainer kit.
Step3: if completed successfully > go to simulation > click source file > right click > new source > select VHDL test bench > create simulation file name > next > select source file > next > finish.
Step4: select simulation file > Isim simulator > click behavioral check syntax > right click > run > if successfully completed. click simulation behavioral > right click > run > wait few seconds > will open new tap.
Step5: click object name > right click > select force constant >
NOTE: if you want image file > click print screen > open MS paint > cnt +v > save
if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok
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