AIM:
To develop a VHDL code for blinking an LED's through 4bit binary up counter in a FPGA kit.
APPARATUS REQUIRED:
Xilinx V14.7 software
FPGA Trainer kits
CONNECTION DIAGRAMS:
TRUTH TABLES:
FLOW CHART:
PROGRAMS CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity code is
port ( clock : in std_logic;
rst:in std_logic;
q : out std_logic_vector(3 downto 0));
end code;
architecture Behavioral of code is
begin
process(clock ,rst)
variable qtemp: std_logic_vector(3 downto 0);
begin
if (rst='1') then
qtemp := "0000";
elsif clock'event and clock = '1' then
if qtemp < 16 then
qtemp:=qtemp+'1';
else
qtemp := "0000";
end if;
end if;
q<= qtemp;
end process;
end Behavioral;
Step2: next > finish > go to project > new source > select VHDL module > create file name> next > select input and output > next > finish> write program > if done write programs > click synthesis > right click> run.
Step3: go to user constraints > select I/O pin planning and right click > run > yes. wait few seconds. will open new tap like this.
Step4: Assign input and output of the trainer kit pinouts > go to file > select save to constraints and close that tap. select implementation design and right click > run. select generate programming and right click > run. if you completed those three option with green tik. select configure device and right click >run. will open new tap. double click boundary scan > ok. connect FPGA Trainer kit to PC system through parallel port or usb > right click centre point of the blue colour line > select initialize chain > then connected your FPGA Trainer kit.
Step5: open .bit file and load it > now you check the output result of the FPGA Trainer kit.
NOTE: if you want image file > click print screen > open MS paint > cnt +v > save
if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok
To develop a VHDL code for blinking an LED's through 4bit binary up counter in a FPGA kit.
APPARATUS REQUIRED:
Xilinx V14.7 software
FPGA Trainer kits
CONNECTION DIAGRAMS:
PROGRAMS CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity code is
port ( clock : in std_logic;
rst:in std_logic;
q : out std_logic_vector(3 downto 0));
end code;
architecture Behavioral of code is
begin
process(clock ,rst)
variable qtemp: std_logic_vector(3 downto 0);
begin
if (rst='1') then
qtemp := "0000";
elsif clock'event and clock = '1' then
if qtemp < 16 then
qtemp:=qtemp+'1';
else
qtemp := "0000";
end if;
end if;
q<= qtemp;
end process;
end Behavioral;
PROCEDURES:
Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next > select proper project settings> we use spartan 3E trainer kit.
Step3: go to user constraints > select I/O pin planning and right click > run > yes. wait few seconds. will open new tap like this.
Step4: Assign input and output of the trainer kit pinouts > go to file > select save to constraints and close that tap. select implementation design and right click > run. select generate programming and right click > run. if you completed those three option with green tik. select configure device and right click >run. will open new tap. double click boundary scan > ok. connect FPGA Trainer kit to PC system through parallel port or usb > right click centre point of the blue colour line > select initialize chain > then connected your FPGA Trainer kit.
Step5: open .bit file and load it > now you check the output result of the FPGA Trainer kit.
NOTE: if you want image file > click print screen > open MS paint > cnt +v > save
if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok
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