EXP-12 SIMULATION OF VHDL TEST BENCH CODE FOR TESTING A GATE

AIM:
       To develop a VHDL test bench code for logic gates.

APPARATUS REQUIRED:
      Xilinx V14.7 software

CONNECTION DIAGRAMS:

LOGIC DIAGRAMS:

PROGRAMS CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity gate_m is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           y_and,y_or,y_nand,y_nor,y_xor : out  STD_LOGIC);
end gate_m;

architecture Behavioral of gate_m is

begin
y_and <= a and b;
y_or <= a or b;
y_nand <= a nand b;
y_nor <= a nor b;
y_xor <= a xor b;

end Behavioral;

SIMULATION OUTPUT:

PROCEDURES:
Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next >  select proper project settings> we use spartan 3E trainer kit.

Step2: next > finish > go to project > new source > select VHDL module > create file name> next > select input and output > next > finish> write program > if done write programs > click synthesis > right click> run.

Step3: if completed successfully > go to simulation > click source file > right click > new source > select VHDL test bench > create simulation file name > next > select source file > next > finish.

Step4: select simulation file > Isim simulator > click behavioral check syntax > right click > run > if successfully completed. click simulation behavioral > right click > run > wait few seconds > will open new tap.

Step5: click object name > right click > select force constant >

Step6: set all input value > click Run for  the time specified on the toolbar> check simulation output in this screen

NOTE: if you want image file > click print screen  > open MS paint > cnt +v > save
           if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok