EXP-14 VHDL IMPLEMENTATION FOR SPELLER WITH AN ARRAY OF LEDS

AIM:
       To develop a  VHDL code for a 5bit johnson counter

APPARATUS REQUIRED:
        Xilinx V14.7 software
        FPGA Trainer kit

CONNECTION DIAGRAMS:

TRUTH TABLES:

FLOW CHART:

PROGRAMS CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity first is

port ( clk : in std_logic;
Reset: in std_logic;
output : out std_logic_vector(4 downto 0));
end first;

architecture Behavioral of first is

signal temp: std_logic_vector(4 downto 0):="00000";

begin

process(clk, Reset)

variable i,k : integer := 0;

begin

if Reset = '1' then

temp <= "00000";

elsif clk'event and clk = '1' then

if i < 50000000 then

i := i + 1;

elsif i = 50000000 then

temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(4) <= temp(3);
temp(0) <= not temp(4);
i:=0;

end if;
end if;
end process;
output <= temp;
End Behavioral;

PROCEDURES:

Step1: Open xilinx software > go to file > new project > create source file name> select specific folder> next >  select proper project settings> we use spartan 3E trainer kit.

Step2: next > finish > go to project > new source > select VHDL module > create file name> next > select input and output > next > finish> write program > if done write programs > click synthesis > right click> run.

Step3: go to user constraints > select I/O pin planning and right click > run > yes. wait few seconds. will open new tap like this.

Step4:  Assign input and output of the trainer kit pinouts > go to file > select save to constraints and close that tap. select implementation design and right click > run. select generate programming and right click > run. if you completed those three option with green tik. select configure device and right click >run. will open new tap. double click boundary scan >  ok. connect FPGA Trainer kit to PC system through parallel port or usb > right click centre point of the blue colour line > select initialize chain > then connected your FPGA Trainer kit.

Step5: open .bit file and load it > now you check the output result of the  FPGA Trainer kit.

NOTE: if you want image file > click print screen  > open MS paint > cnt +v > save
           if you want PDF file > file > print > select doPDF printer > create pdf file name + quality> ok